Field
The present disclosure relates generally to an interface between processors and a peripheral devices and, more particularly, to improving data communications capabilities of a serial bus.
Background
The Inter-Integrated Circuit serial bus, which may also be referred to as the I2C bus or the I2C bus, is a serial single-ended computer bus that was intended for use in connecting low-speed peripherals to a processor. The I2C bus is a multi-master bus in which each device can serve as a master and a slave for different messages transmitted on the I2C bus. The I2C bus can transmit data using only two bidirectional open-drain connectors, including a Serial Data Line (SDA) and a Serial Clock Line (SCL). The connectors typically include signal wires that are terminated by pull-up resistors. Original implementations of I2C supported data signaling rates of up to 100 kilobits per second (100 kbps) in standard-mode (Sm) operation, with more recent standards supporting speeds of 400 kbps in fast-mode (Fm) operation, and 1 megabit per second (Mbps) in fast-mode plus (Fm+) operation.
In some systems and apparatus, however, higher bandwidths are required to support communications between certain types of devices. For example, mobile communications devices such as cellular phones may employ multiple devices, including cameras, displays and various communications interfaces that consume significant bandwidth. Higher bandwidths may be difficult to obtain when mixed signaling, including signaling according to conventional I2C protocols, is to be used in order to maintain compatibility with legacy devices. For example, it may be difficult to determine whether I2C devices can coexist on a serial bus that is used by enhanced devices to transmit data and commands at higher bit rates than the I2C devices can handle. Accordingly, there exists an ongoing need for providing optimized communications on serial interfaces configured as a bus connecting master and slave components within a mobile device.